Flip chip electrical interconnection by selective electroplating and bonding

This work presents a parallel electrical interconnection process by means of flip-chip, selective electroplating and bonding. The electrical interconnection lines are built on a glass substrate made of 500/2000 Å of Cr/Au with 3150 lm in length and 10 lm in width. Two silicon chips are processed as the device chips to be electrically interconnected. It has been demonstrated that 98 out of 102 interconnects are established in parallel with a successful rate of 96% and the average resistance of the electroplating bond is 12 W. This process has potential applications in replacing the conventional, serial wire bonding or tape automated bonding (TAB) process for massive interconnection requirements in IC or MEMS devices. Reliability test is also performed by putting the interconnects into boiling liquid nitrogen ()195 C) repeatedly. It is found that 100% of the interconnects survive after 2 cycles of the quenching process.